semiconductor
Source: https://semiwiki.com/semiconductor-services/in2fab/374736-migration-feasibility-study/ Moving semiconductor IP to a new process technology is often treated as a redesign problem. For analog and mixed-signal designs, however, starting again from the schematic can overlook an asset: the engineering knowledge embedded in the existing physical layout. 반도체 IP를 새로운 공정
semiconductor
Source: https://semiwiki.com/semiconductor-manufacturers/teradyne/374603-teradyne-unveils-magnum-e2-for-the-next-wave-of-ai-memory/ Teradyne has announced Magnum E2, a memory test system designed to address the increasingly demanding interfaces used in artificial intelligence and high performance computing. The platform targets advanced DRAM and flash technologies, including LPDDR6, DDR6, GDDR7, and NAND flash, while combining engineering and
semiconductor
Source: https://semiwiki.com/semiconductor-manufacturers/vsora/374585-vsoras-sandra-rivera-on-the-inference-era-demand-is-real-but-not-everyone-survives/ Sandra Rivera, Chair of VSORA, joined Bloomberg’s The Close in July for an interview on the current state of AI. What follows is a summary of that conversation. VSORA의 의장인 산드라 리베라(Sandra Rivera)는 지난 7월 블룸버그의 ‘더 클로즈(The Close)
semiconductor
Source: https://semiwiki.com/semiconductor-manufacturers/intel/374536-intels-open-software-blueprint-why-production-ai-needs-more-than-gpus/ Intel’s strategic argument about enterprise AI is that the value of a model depends on the system that surrounds it. In an article by executives Bill Pearson and Anil Nanduri, the company positions open software as the connective tissue linking CPUs, GPUs,
semiconductor
Source: https://semiwiki.com/eda/clockedge/374633-cto-interview-with-dr-zakir-syed-of-clockedge/ Dr. Zakir Syed is Co-founder and Chief Technology Officer of ClockEdge, where he has played a central role in developing specialized simulation technology for advanced semiconductor clock networks. He brings more than 30 years of experience in electronic design automation and semiconductor verification.
semiconductor
Source: https://semiwiki.com/ip/chipsmedia/374498-chipsmedia-targets-ai-memory-bottlenecks-with-new-compression-ip/ Chips&Media has announced a data compression technology aimed at one of the constraints in artificial intelligence hardware: moving data fast enough to keep processors busy. The South Korean semiconductor intellectual property supplier says its new Feature Map Compression IP marks an
semiconductor
Source: https://semiwiki.com/artificial-intelligence/374757-overcoming-the-edge-ai-power-wall-with-low-voltage-foundation-ip/ As artificial intelligence (AI) workloads migrate to endpoint hardware, edge AI devices face immense pressure to deliver real-time inference within highly restrictive power and thermal envelopes. Traditional silicon scaling no longer yields the power-density returns it once did. To compensate, engineering teams are turning
semiconductor
Source: https://semiwiki.com/eda/374576-keysight-advances-its-design-software-with-agentic-ai/ Keysight Technologies is opening a new route for artificial intelligence into radio frequency engineering. Announced on October 6, 2026, its latest software capabilities let engineers connect their own AI agents and large language models to Advanced Design System (ADS) 2027. Agents can help generate
semiconductor
Source: https://semiwiki.com/events/374512-dac-2027-opens-call-for-contributions-as-ai-reshapes-chip-design/ The Design Automation Conference is the premier semiconductor ecosystem conference. I have attended 43 DACs including the most recent one in Long Beach. My first DAC was in Albuquerque NM. It was a month after my University so i was still in college mode.
semiconductor
Source: https://semiwiki.com/eda/374909-chipagents-and-nvidia-put-autonomous-chip-design-to-the-test/ ChipAgents has introduced Build-A-Chip-Bench, a benchmark developed with NVIDIA to evaluate whether AI agents can complete digital chip design tasks from specification through physical implementation. The initiative measures progress beyond generating hardware code, asking whether autonomous systems can deliver verified layouts while satisfying interconnected
semiconductor
Source: https://semiwiki.com/lithography/374764-hyper-na-euv-the-next-frontier-in-chipmaking-could-arrive-in-2036/ Hyper-NA EUV could be ready around 2036, based on the roughly ten-year development outlook reported by ASML and Zeiss engineers in October 2026. ASML과 자이스(Zeiss) 엔지니어들이 2026년 10월에 보고한 약 10년의 개발 전망을 바탕으로 할 때, 하이퍼-NA(Hyper-NA) EUV는 2036년경에 준비될 수 있습니다.
semiconductor
Source: https://semiwiki.com/semiconductor-manufacturers/tsmc/374104-tsmc-2026-oip-ecosystem-forum-summary/ TSMC’s 2026 Open Innovation Platform Forum presented artificial intelligence as the force reshaping semiconductor design. Its central argument is that faster chips will require progress across the whole system: logic, memory, packaging, interconnects, power delivery and design methods. TSMC places its partner