SemiWiki

Hyper-NA EUV: The Next Frontier in Chipmaking Could Arrive in 2036

semiconductor

Hyper-NA EUV: The Next Frontier in Chipmaking Could Arrive in 2036

Source: https://semiwiki.com/lithography/374764-hyper-na-euv-the-next-frontier-in-chipmaking-could-arrive-in-2036/ Hyper-NA EUV could be ready around 2036, based on the roughly ten-year development outlook reported by ASML and Zeiss engineers in October 2026. ASML과 자이스(Zeiss) 엔지니어들이 2026년 10월에 보고한 약 10년의 개발 전망을 바탕으로 할 때, 하이퍼-NA(Hyper-NA) EUV는 2036년경에 준비될 수 있습니다.

By Jeongwoo Heo
TSMC 2026 OIP Ecosystem Forum Summary

semiconductor

TSMC 2026 OIP Ecosystem Forum Summary

Source: https://semiwiki.com/semiconductor-manufacturers/tsmc/374104-tsmc-2026-oip-ecosystem-forum-summary/ TSMC’s 2026 Open Innovation Platform Forum presented artificial intelligence as the force reshaping semiconductor design. Its central argument is that faster chips will require progress across the whole system: logic, memory, packaging, interconnects, power delivery and design methods. TSMC places its partner

By Jeongwoo Heo
Data Center Energy Trends Force a Rethink of Chip Power Delivery

semiconductor

Data Center Energy Trends Force a Rethink of Chip Power Delivery

Source: https://semiwiki.com/semiconductor-manufacturers/intel/374308-data-center-energy-trends-force-a-rethink-of-chip-power-delivery/ Intel Foundry published a two article series on chip power delivery that are worth reading. Here is a quick summary: 인텔 파운드리(Intel Foundry)는 칩 전력 공급에 관한 주목할 만한 2부작 기사 시리즈를 발표했습니다. 주요 요약은 다음과 같습니다. Artificial intelligence is changing

By Jeongwoo Heo
The silent killer of analog reliability: Why SPICE misses floating net

semiconductor

The silent killer of analog reliability: Why SPICE misses floating net

Source: https://semiwiki.com/eda/siemens-eda/374257-the-silent-killer-of-analog-reliability-why-spice-misses-floating-net/ By Bhanu Pandey The semiconductor industry is currently facing a significant challenge in functional verification. According to the most recent Wilson Research Group / Siemens EDA Functional Verification Study, first-silicon success rates have hit a historic low, with nearly 68% of designs requiring two

By Jeongwoo Heo
Built to Deliver the Answer, Not to Train the Model

semiconductor

Built to Deliver the Answer, Not to Train the Model

Source: https://semiwiki.com/semiconductor-manufacturers/vsora/374232-built-to-deliver-the-answer-not-to-train-the-model/ For more than a decade, the AI hardware industry focused mainly on model training, while inference represented a smaller share of overall demand. That balance is changing as trained models are deployed widely in recommendation engines, content-generation systems, transcription and translation services, and

By Jeongwoo Heo
From Simulation to Deployment: Why Physical AI Matters

semiconductor

From Simulation to Deployment: Why Physical AI Matters

Source: https://semiwiki.com/eda/synopsys/373937-from-simulation-to-deployment-why-physical-ai-matters/ Artificial intelligence is moving beyond the screen. The attached presentation describes a shift from systems that generate text, images, and code to systems that can perceive their surroundings and take action. These systems could guide robots, vehicles, factory equipment, medical devices, and critical

By Jeongwoo Heo
Significant Performance Gains Reinforce Imagination’s GPU-First Strategy

semiconductor

Significant Performance Gains Reinforce Imagination’s GPU-First Strategy

Source: https://semiwiki.com/ip/imagination-technologies/373826-significant-performance-gains-reinforce-imaginations-gpu-first-strategy/ Imagination Technologies’ first performance figures for its E-Series GPU IP turn its “GPU-first” strategy from an architectural proposition into a measurable product claim. The company is arguing that edge systems do not need separate, lightly utilised blocks for graphics, general compute and artificial

By Jeongwoo Heo
AI-EDA Agents Can Prove Their Value

semiconductor

AI-EDA Agents Can Prove Their Value

Source: https://semiwiki.com/eda/374287-ai-eda-agents-can-prove-their-value/ Before EDA becomes AI-native, focused agents have a window to prove measurable engineering value inside existing design flows. EDA(전자 설계 자동화)가 근본적으로 AI 네이티브(AI-native)한 구조로 완전히 전환되기 전까지, 특정 영역에 집중된 에이전트들은 기존 설계 워크플로 안에서 측정 가능한 엔지니어링적 가치를

By Jeongwoo Heo
Intel Foundry: AI performance now depends on the whole system

semiconductor

Intel Foundry: AI performance now depends on the whole system

Source: https://semiwiki.com/semiconductor-manufacturers/intel/374240-intel-foundry-ai-performance-now-depends-on-the-whole-system/ For decades, chipmakers improved computing performance largely by putting more capable circuitry on a piece of silicon. That remains important, but AI is exposing its limits. Large models demand enormous amounts of data movement, sustained power and effective cooling. A fast processor cannot

By Jeongwoo Heo
TSMC’s AI Design Kit: Bringing Agentic AI Into Chip Design

semiconductor

TSMC’s AI Design Kit: Bringing Agentic AI Into Chip Design

Source: https://semiwiki.com/semiconductor-manufacturers/tsmc/374098-tsmcs-ai-design-kit-bringing-agentic-ai-into-chip-design/ TSMC is introducing an AI Design Kit, or ADK, to help artificial intelligence tools make better use of its semiconductor manufacturing knowledge. The idea is to give AI agents that run chip-design workflows a technology-specific foundation, so they can adjust designs toward performance,

By Jeongwoo Heo