Jeongwoo Heo

Hyper-NA EUV: The Next Frontier in Chipmaking Could Arrive in 2036

semiconductor

Hyper-NA EUV: The Next Frontier in Chipmaking Could Arrive in 2036

Source: https://semiwiki.com/lithography/374764-hyper-na-euv-the-next-frontier-in-chipmaking-could-arrive-in-2036/ Hyper-NA EUV could be ready around 2036, based on the roughly ten-year development outlook reported by ASML and Zeiss engineers in October 2026. ASML과 자이스(Zeiss) 엔지니어들이 2026년 10월에 보고한 약 10년의 개발 전망을 바탕으로 할 때, 하이퍼-NA(Hyper-NA) EUV는 2036년경에 준비될 수 있습니다.

By Jeongwoo Heo
TSMC 2026 OIP Ecosystem Forum Summary

semiconductor

TSMC 2026 OIP Ecosystem Forum Summary

Source: https://semiwiki.com/semiconductor-manufacturers/tsmc/374104-tsmc-2026-oip-ecosystem-forum-summary/ TSMC’s 2026 Open Innovation Platform Forum presented artificial intelligence as the force reshaping semiconductor design. Its central argument is that faster chips will require progress across the whole system: logic, memory, packaging, interconnects, power delivery and design methods. TSMC places its partner

By Jeongwoo Heo
Data Center Energy Trends Force a Rethink of Chip Power Delivery

semiconductor

Data Center Energy Trends Force a Rethink of Chip Power Delivery

Source: https://semiwiki.com/semiconductor-manufacturers/intel/374308-data-center-energy-trends-force-a-rethink-of-chip-power-delivery/ Intel Foundry published a two article series on chip power delivery that are worth reading. Here is a quick summary: 인텔 파운드리(Intel Foundry)는 칩 전력 공급에 관한 주목할 만한 2부작 기사 시리즈를 발표했습니다. 주요 요약은 다음과 같습니다. Artificial intelligence is changing

By Jeongwoo Heo
The silent killer of analog reliability: Why SPICE misses floating net

semiconductor

The silent killer of analog reliability: Why SPICE misses floating net

Source: https://semiwiki.com/eda/siemens-eda/374257-the-silent-killer-of-analog-reliability-why-spice-misses-floating-net/ By Bhanu Pandey The semiconductor industry is currently facing a significant challenge in functional verification. According to the most recent Wilson Research Group / Siemens EDA Functional Verification Study, first-silicon success rates have hit a historic low, with nearly 68% of designs requiring two

By Jeongwoo Heo